1. Field of the Invention
The present invention provides a structure of stacking chips and a method for manufacturing the same, with the structure of stacking chips comprising signal processing chips and optical chips.
2. Descriptions of the Related Art
With the evolution of people's living habits and the advancement of manufacturing technologies, imaging sensors have been generally used in the daily life. The imaging sensors that have already been known are, for example, complementary metal-oxide semiconductor (CMOS) imaging sensors and charge coupled device (CCD) imaging sensors. The CMOS imaging sensors have advantages, such as a lower price and power consumption, and are usually suitable for use in low-level products. The CCD imaging sensors can capture images of a better quality, which is the reason why they have been the primary products in the market of high-level imaging sensors.
However, combining digital signal processor (DSP) chips with the CMOS imaging sensors can compensate for the shortcomings of the CMOS imaging sensors. In detail, the DSP chips can simulate human eyes to process what photosensitive components cannot identified, and further contribute to the imaging performance of the CMOS imaging sensors by using an algorithm. Therefore, the modules combining the CMOS imaging sensors and the DSP chips have been gradually used in high-resolution portable products such as digital video cameras and digital cameras.
With reference to FIGS. 1A to 1C, a conventional package structure 1 for CMOS imaging sensor (CIS) chips 11 and DSP chips 12, and its manufacturing process of the package structure 1 are shown therein. As shown in FIG. 1A, multiple imaging sensor chips 11 are formed on a wafer 13 and then sliced into individual imaging sensor chips 11, and each imaging sensor chip 11 has multiple first contacts 111 distributed at two sides of the imaging sensor chip 11. Likewise, as shown in FIG. 1B, multiple DSP chips 12 are also formed on a wafer 14 and then sliced into individual DSP chips 12, and each DSP chips 12 has multiple second contacts 121 distributed at the two sides of the DSP chip 12.
With reference to FIG. 1C, in the prior art, the individual sliced imaging sensor chips 11 and the individual DSP chips 12 transversely aligned and arranged on a substrate, and then the first contacts 111 and the second contacts 121 are sequentially electrical connected through wire bonding.
Conceivably in the prior art, first the wafer 13 and the wafer 14 are sliced respectively to form the individual imaging sensor chips 11 and the individual DSP chips 12 which are corresponding sizes. Then the imaging sensor chips 11 and the DSP chips 12 are attached respectively and the imaging sensor chips 11 and the DSP chips 12 are connected through wire bonding. The prior art requires a complex manufacturing process and a long production cycle, which increases manufacturing costs. In addition, the imaging sensor chips 11 and the DSP chips 12 are transversely arranged on the substrate side by side and, thus, it's occupied a relatively larger area, and the reliability of wire bonding is poor. Consequently, the prior art tends to cause poor contact or poor stability.
In view of this, an urgent need exists in the art to provide a structure of stacking chips and a method for manufacturing the same which can improve the manufacturing process, reduce the volume and occupied area and increase the reliability.